1. Technical Field
The present invention relates to a semiconductor apparatus, and more particularly, to technologies for configuring a clock generation circuit and a delay locked loop.
2. Related Art
A semiconductor apparatus operates in synchronization with a periodic pulse signal such as a clock signal in order to increase an operation speed and ensure efficient internal operations. Most semiconductor apparatuses use externally supplied clock signals or internally generated clock signals dependent on the occasion.
An external clock signal inputted to a semiconductor apparatus becomes delayed inside the semiconductor apparatus, and thus in cases where data is outputted using a delayed clock signal, the outputted data is not synchronized with the external clock signal, which is problematic. Therefore, the semiconductor apparatus compensates for difference in timing between the external clock signal and the internal clock signal by using a delay locked loop (DLL) or a phase locked loop (PLL).
As frequencies of external clock signals gradually increase to accommodate high speed operations, it becomes increasingly difficult to generate internal clock signals with desirable phases.